1. Field of the Invention
The present invention relates to a data transfer device with a post charge logic. In particular, it relates to a data transfer device with a post charge logic, which initializes data lines in a memory device after data is transferred.
2. Description of the Prior Art
In general, a post charge operation is to initialize data lines by using the signals transferred on the data lines, after a data receiving circuit has received data outputted from a data transferring circuit through the data lines.
FIG. 1 represents a circuit diagram of a conventional data transfer device with a post charge logic circuit. In the diagram, each of the data bus sense amplifiers 10 and 40 is coupled to the corresponding receiving parts 20 and 50 through corresponding data line pairs DL1, DL2 and DL3, DL4.
The data bus sense amplifiers 10 and 40 transfer high/low level data to the receiving part 20 and 50 through the corresponding data line pairs DL1, DL2 and DL3, DL4. This is conducted by controlling the data driving elements N1, N2, N3, and N4 provided between the data lines DL1, DL2, DL3, and DL4 and ground voltage.
As shown in FIG. 1, post charge logic circuits 30 and 32 are provided on the data line pair DL1 and DL2 to initialize the data lines after the data has been transferred from the data bus sense amplifier 10 to the data lines. Post charge logic circuits 60 and 62 are provided on the data line pair DL3 and DL4 to initialize the data lines after the data has been transferred from the data bus sense amplifier 40 to the data lines.
The post charge logic circuit 30 comprises an inverter circuit 30a for receiving data on the data line DL1, delay circuit 30b for delaying the output signal from the inverter 30a for a predetermined time, an inverter circuit 30c for receiving the output signal from the delay circuit 30b, and a switching element P1 (wherein P1 is a PMOS transistor) for controlling the voltage level on the data line DL1 in response to an output signal from the inverter 30c. The construction of the other post charge logic circuits 32, 60, and 62 is identical with that of the post charge logic circuit 30.
The operation of the conventional data trnsfer device with a post charge logic in consideration of the operations of the data bus sense amplifier and the receiving part will be expalined hereinafter in detail.
The operation which transfers high level data to the receiving parts will be illustrated. At the beginning, the voltage levels of the data lines DL_1, and DL_2 are predetermined by a pheriperal circuit (not shown), and generally are set to a high level. When one (for example, N1) of the data driving elements N1 and N2 is turned on in response to the output signal from the data bus sense amplifier 10, the voltage level of the data line DL1 is changed from a high level to a low level.
In the beginning, the PMOS transistor P1 within the post charge logic circuit 30 is turned off until the data line DL1 has changed from a high level to a low level, thus the voltage of the data line DL1 is high level. When the voltage level of the data line DL1 has changed to a low level, the PMOS P1 will be turned on after a time lapse.
Therefore, the voltage level of the data line DL1 is initialized in response to the turned on PMOS transistor P1 after the signal of high data has been transferred to the receiving part.
On the contrary, the operation which transfers high level data to the receiving parts will be illustrated. At the beginning, the voltage levels of the data lines DL_1, and DL_2 are predetermined by a pheriperal circuit (not shown), and generally are set to a high level. When one (for example, N2) of the data driving elements N1 and N2 is turned on in response to the output signal from the data bus sense amplifier 10, the voltage level of the data line DL2 is changed from a high level to a low level. The PMOS transistor P2 within the post charge logic circuit 32 is turned off until the data line DL2 has changed from a high level to a low level, thus the voltage of the data line DL2 is high level.
When the voltage level of the data line DL2 has changed to a low level, the PMOS P2 will be turned on after a time lapse.
Therefore, the voltage level of the data line DL2 is initialized in response to the turned on PMOS transistor P2 after the signal of high data has been transferred to the receiving part.
The operation of the other data bus sense amplifier 40 and receving part 50 is identicel with that of the data transfer device illustrated above. In general, there is a plurality of data bus sense amplifiers and receving parts in the data transfer device.
As shown in FIG. 1 and illustrated above, the conventional data transfer device comprises a plurality of post charge logic circuits, each of which is provided on the each data line, resulting in an increase in the power consumption and an increase in a layout area.